1. Field of the Invention
The present invention generally relates to memory systems for digital computers and, more particularly, to a new memory design which facilitates incremental fetch and store requests off an applied base address request.
2. Background Description
In cache memories, sequential instructions are retrieved from incremental address locations, J, J+1, etc., each cycle. With the exception of a branch, instructions reside in sequential memory locations because program flow is purely sequential. Therefore, instructions can be sequentially prefetched from cache and stored in an instruction queue. Similarly, data request usually have a sequential ordering, but certain situations arise in which it is convenient to store and retrieve data using an address with stride dimension other than +1; for example, +N or -N, where N equals 1, 2, 3, etc. It is desirable to exploit this naturally arising order of memory requests.